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STV7710/WAF
Vacuum Fluorescent Display (VFD) Driver
FEATURES
96 Outputs VFD Driver 90V Absolute Maximum Supply 3.3V/5V compatible logic -40/30mA source/sink output MOS -50/50mA source/sink output diode 1 bit data bus (40MHz) BCD process Packaging: Die Form
DESCRIPTION
STV7710/WAF is a driver for vacuum fluorescent display (VFD) designed in the ST proprietary BCD high voltage technology. Using a 1 bit wide data bus, it can control 96 high current & high voltage outputs. The STV7710/WAF is supplied with a separated 70V power output supply. All command inputs are CMOS and 3.3V logic levels compatible.
ORDERING INFORMATION
Ordering code
STV7710/WAF
Package
Bare die
April 2004
1/19
STV7710/WAF
Table of content
Chapter 1 Chapter 2 Chapter 3
3.1 3.2
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 DIE PIN OUT / DIE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 MECHANICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Alignment marks specification .............................................................................................. 5 Pads specification ................................................................................................................ 5
Chapter 4
4.1 4.2 4.3
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin description ...................................................................................................................... 9 Data bus configuration ......................................................................................................... 9 Description ......................................................................................................................... 10
Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 AC TIMING REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 AC TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 INPUT/OUPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2/19
STV7710/WAF
BLOCK DIAGRAM
1
BLOCK DIAGRAM
Figure 1: STV7710/WAF block diagram
CLK
F/R
TEST
DATA_A 96bit Shift register
DATA_B
P1
P96
Latch STB Q1 Q2 Q95 Q96
VSSLOG
VSSSUB POC & & & & VCC
BLK & & & &
STV7710/WAF
VSSP
OUT1
OUT96
VPP
3/19
DIE PIN OUT / DIE DESCRIPTION
STV7710/WAF
2
DIE PIN OUT / DIE DESCRIPTION
Figure 2: STV7710/WAF die pinout
2.07
OUT54 OUT43
OUT55 OUT56 OUT57
OUT42 OUT41 OUT40
y
5.89
0/0
x
OUT95 OUT96 VPP VPP VSSP VSSP
OUT2 OUT1 VPP VPP VSSP VSSP
VSSLOG
4/19
VSSLOG
VSSSUB
DATA_B DATA_A
POC
TEST
VCC
CLK
STB
BLK
F/R
STV7710/WAF
MECHANICAL SPECIFICATION
3
3.1
MECHANICAL SPECIFICATION
Alignment marks specification
Figure 3: Alignment marks
min. 0.35 min 0.1 0.25 Patterning restricted area
min. 0.35
min 0.1
0.25
0.15
3.2
Pads specification
The reference is the centre of the die (x=0, y=0)
Table 1: Top side from left to right Name
OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43
Centre: X
-773.67 -670.48 -567.29 -464.1 -360.91 -257.72 -154.53 -51.34 51.85 155.04 258.23 361.42
Centre: Y
2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11
Size: x
76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
0.15
SIze: y
92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
5/19
MECHANICAL SPECIFICATION
Table 2: Bottom side from right to left Name
VSSLOG CLK F/R POC VCC STB BLK DATA_A DATA_B VSSSUB TEST VSSLOG
STV7710/WAF
Centre: X
771.63 669.54 566.35 463.16 359.97 257.63 154.44 51.25 -119.85 -567.88 -669.54 -771.63
Centre: Y
-2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23
Size: x
76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
SIze: y
92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
Table 3: RIGHT SIDE from top to bottom Name
OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21
Centre: X
887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61
Centre: Y
2050.11 1946.92 1843.73 1740.54 1638.88 1535.69 1432.50 1329.31 1226.12 1122.93 1019.74 916.55 813.36 710.17 606.98 503.79 400.60 297.41 194.22 91.03 -12.15 -115.34
Size: x
92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: y
76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
6/19
STV7710/WAF
MECHANICAL SPECIFICATION
Table 3: RIGHT SIDE from top to bottom Name
OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VPP VPP VSSP VSSP
Centre: X
887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61
Centre: Y
-218.53 -321.72 -424.91 -528.10 -631.29 -734.48 -837.67 -940.86 -1044.05 -1147.24 -1250.43 -1353.62 -1456.81 -1560.00 -1663.19 -1766.38 -1869.57 -1972.76 -2075.95 -2179.14 -2282.16 -2385.35 -2488.46 -2591.65
Size: x
92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: y
76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
Table 4: LEFT SIDE from bottom to top Name
VSSP VSSP VPP VPP OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89
Centre: X
-887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61
Centre: Y
-2591.65 -2488.46 -2385.35 -2282.16 -2179.14 -2075.95 -1972.76 -1869.57 -1766.38 -1663.19 -1560.00 -1456.81
Size: x
92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: y
76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
7/19
MECHANICAL SPECIFICATION
Table 4: LEFT SIDE from bottom to top Name
OUT88 OUT87 OUT86 OUT85 OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 OUT71 OUT70 OUT69 OUT68 OUT67 OUT66 OUT65 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55
STV7710/WAF
Centre: X
-887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61
Centre: Y
-1353.62 -1250.43 -1147.24 -1044.05 -940.86 -837.67 -734.48 -631.29 -528.10 -424.91 -321.72 -218.53 -115.34 -12.15 91.03 194.22 297.41 400.60 503.79 606.98 710.17 813.36 916.55 1019.74 1122.93 1226.12 1329.31 1432.50 1535.69 1638.88 1740.54 1843.73 1946.92 2050.11
Size: x
92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: y
76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
8/19
STV7710/WAF
CIRCUIT DESCRIPTION
4
4.1
CIRCUIT DESCRIPTION
Pin description
Table 5: STV7710/WAF pin description Symbol
OUT(01-96) VSSP VPP BLK POC F/R VCC VSSLOG VSSSUB CLK STB DATA_A DATA_B TEST
Function
Output Ground Supply Input Input Input Supply Ground Ground Input Input Input/output Input/output Input Power output
Description
Ground of power outputs High voltage supply of power outputs Blanking input Power output control input Selection of shift direction 5V logic supply Logic ground Substrate ground Clock of data shift register Latch of data to outputs Shift register input Shift register output Test input pin
4.2
Data bus configuration
Table 6: STV7710/WAF data bus configuration
F/R Input CLK
H DATA_A Output L DATA_B Output
Data shift 01
01 96
Output 91
91 06
02
02 95
03
03 94
04
04 93
05
05 92
06
06 91
...
92
92 05
93
93 04
94
94 03
95
95 02
96
96 01 DATA_B Forward shift DATA_A Reverse shift
This table describes the position of the first data sampled by the first rising edge of the CLK signal.
9/19
CIRCUIT DESCRIPTION
STV7710/WAF
4.3
Description
STV7710/WAF includes all the logic and power circuits necessary to drive electrodes of a vacuum fluorescent display (VFD). Binary values of each pixel of the displayed line are loaded into the shift register DATA_A/B data bus. Data is shifted at each low to high transition of the CLK clock. After 96 shifts, the data is available at the output of the shift register. This output can be used to cascade several Ics to drive higher resolution displays. The forward /reverse (F/R) input is used to select the direction of the shift register. Data input/output status is set according to the selected direction (refer to Table 6). The maximum frequency of the shift clock is 40MHz. When the STB signal is high, data are transferred from the shift register to the latch and power output stages. All the output data are kept memorized and held in the latch stage when the latch input STB is set at low level. Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the application. Also, make sure that TEST input pin is connected to ground (Figure 8). STV7710/WAF is supplied with a 5 volt power supply. All the logic inputs can be driven either by 5V CMOS logic, or by 3.3V CMOS logic.
Table 7: Shift register truth table Input F/R
H H L L
Data-in / Data-out Shift register function CLK
H or L
DATA_A
Data-in Data-out -
DATA_B
Data-out Data-in Forward shift Steady Reverse shift Steady
H or L
Table 8: Power output truth table TEST
L L L L L
Qn
X X X L H
STB
X X L H H
BLK
H L L L L
POC
X L H H H
Driver Output
all "Low" all "High" Qn L H
Comments
Output at low level Output at high level Data latched Data transfered Data transfered
10/19
STV7710/WAF
ABSOLUTE MAXIMUM RATINGS
5
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc Vpp Vin Ipout Tjmax Tstg Vout
Parameter
Logic supply range Driver supply range Logic input voltage range Driver output current (Note 1)(Note 2) Maximum junction temperature Storage temperature range Output power voltage range
Value
-0.3, +7 -0.3, +90 -0.3, Vcc+0.3 -40 / +30 125 -30, +150 -0.3, +90
Unit
V V V mA C C V
Note: 1 Through one power output. 2 Through one power output for all power outputs (see Figure 5:Test configuration page16) with Junction temperature lower than or equal to Tjmax
ESD Susceptibility Human Body Model: 100pF; 1.5K All pins withstand 2Kv except Data_A and Data_B: 1.2Kv
11/19
ELECTRICAL CHARACTERISTICS
STV7710/WAF
6
ELECTRICAL CHARACTERISTICS
(Vcc = 5V, Vpp = 70V, Vssp = 0V, Vss = 0V, Tamb = 25C, FCLK = 40 MHz, unless otherwise specified)
Symbol
SUPPLY Vcc Icc Iccl Logic supply voltage Logic supply current (Note 1) Logic Dynamic Supply Current (FCLK=20Mhz) (Note 2) Logic Supply Current (Vih=2.0V) Power output supply voltage Power output supply current (steady outputs) 15 4.50 5 45 20 5.5 100 V A mA A V A
Parameter
Min
Typ
Max
Unit
Icc Vpp Ipph OUTPUT
-
750 70 10
OUT1-OUT96 (Figure 10) Vpouth Power output high level (voltage drop versus Vpp) @Ipouth = - 20mA and Vpp = 70V Vpoutl Vdouth Vdoutl Power output low level @ Ipoutl = + 20mA Output diode voltage drop @ Idouth = + 30mA (Note 3) Output diode voltage drop @ Idoutl = - 30mA (Note 3) -2 7.5 5 1 -1 14 11 2 V V V V
DATA A, DATA B (Figure 9) Voh Vol INPUT CLK, F/R, STB, POC, BLK, DATA_A, DATA B (Figure 7) Vih Vil Iih Iil Cin Input high level Input low level High level input current (Vih >=2.0V) Low level input current (Vil = 0v) Input capacitance (Note 4) 2.0 0.9 5 5 15 V V A A pF Logic output high level @Ioh=-1mA Logic output low level @Iol = 1 mA 4 4.8 0.1 0.4 V V
Note: 1 Logic input levels compatible with 5V CMOS logic 2 All data inputs are commuted at 10MHz 3 see Figure 5:Test configuration page16 4 This parameter is measured during ST's internal qualification which includes temperature characterization on standard and corner batches of the process. This parameter is not tested on the part.
12/19
STV7710/WAF
AC TIMING REQUIREMENTS
7
AC TIMING REQUIREMENTS
(Vcc = 4.5v to 5.5v, Tamb = -20 to +85C, input signals max leading edge & trailing edge (tr, tf) = 5ns)
Symbol
tCLK tWHCLK tWLCLK tSDAT tHDAT tHSTB tSTB tSSTB Data clock period Duration of CLK pulse at high level Duration of CLK pulse at low level Set-up time of data input before low to high clock transition Hold-time of data input after low to high clock transition Hold-time of STB after low to high clock transition
Parameter
Min
25 10 10 5 5 5 10 5
Typ
-
Max
-
Unit
ns ns ns ns ns ns ns ns
STB low level pulse duration STB set-up time before CLK rise
13/19
AC TIMING CHARACTERISTICS
STV7710/WAF
8
AC TIMING CHARACTERISTICS
(Vcc = 5V, Vpp = 70V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb = 25C, FCLK = 40MHz) (Vilmax = 0.2Vcc, Vihmin = 0.8Vcc)
Symbol
tPHL1 tPLH1 tPHL2 tPLH2
Parameter
Delay of power output change after CLK transition - high to low - low to high Delay of power output change after STB transition - high to low - low to high
Min
Typ
Max
Unit
-
35 30
100 100
ns ns
-
95 95
ns ns
tPHL3 tPLH3
Delay of power output change after BLK, POC transition - high to low - low to high 50 50 -
25 20 30 9 5
90 90 200 200 20 12
ns ns ns ns ns ns ns
tR OUT tF OUT tS tR DAT tF DAT tPHL4 tPLH4
Power output rise time (Note 1) Power output fall time (Note 1) Width of the Falling Edge Smooth Shape (not tested) (Note 2) Logic data output rise time (CL = 10pF) Logic data output fall time (CL = 10pF) Delay of logic data output change after CLK transition - high to low - low to high
-
12 13
25 25
ns ns
Note: 1 One output among 96, loading capacitor CL = 50pF, other outputs at low level 2 See Figure 6
14/19
STV7710/WAF
AC TIMING CHARACTERISTICS
Figure 4: AC characteristics waveform
tCLK tWHCLK tWLCLK "1" CLK 50% 50% tSDAT 50% "0" tHDAT "1" DATA_A 50% tPHL4 tF DAT 50% "0"
DATA_B
tSTB
tPLH4
tHSTB
tR DAT "1"
STB 50%
50% "0" tSSTB
tPHL2 90% 10% tPLH2
tPHL1 "1" 90% 10% tPLH1 "0"
OUTn
"1" BLK (POC="L") 50% 50% "0" tPLH3 OUTn 10% tF OUT tR OUT 90% tPHL3 90% 10% "1"
"0"
15/19
AC TIMING CHARACTERISTICS
Figure 5: Test configuration
STV7710/WAF
VPP=VSSP
VPP=VSSP
VDOUTH
IDOUTH
VDOUTL VSSP VSSP
IDOUTL
Output sinking current as positive value, sourcing current as negative value
Figure 6: Zoom for OUTn showing tS and tF OUT
tF OUT OUTn 90%
10% tS
16/19
STV7710/WAF
INPUT/OUPUT SCHEMATICS
9
INPUT/OUPUT SCHEMATICS
Figure 7: CLK, STB, F/R, POC, BLK inputs
VCC VCC
Figure 8: Test pin
VCC VCC
CLK, STB F/R, POC, BLK,
TEST
GNDSUB GNDSUB GNDLOG ! must be grounded in the application
GNDLOG
Figure 9: DATA_A, DATA_B
VCC VCC
Figure 10: Power output
VPP
DATA_A DATA_B
VCC
OUT1 to OUT 96
GNDLOG GNDSUB V SSP
17/19
THERMAL CHARACTERISTICS
STV7710/WAF
10
THERMAL CHARACTERISTICS
STV7710/WAF can be exposed to high temperatures during the manufacturing of the VFD module (display sealing). STV7710/WAF is qualified for a maximum storage temperature of 475C during 30 minutes following the thermal profile described in Figure 11.
Figure 11: Thermal profile applied for internal qualification
Temperature (in Celsius)
500 400 300 200 100 0 0 5 10 15 20 25 30 35 Time (in min.) Thermal profile
18/19
STV7710/WAF
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
19/19

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